
package executestage
import chisel3._
import chisel3.util._
import decoderstage.{GRFReadBus, StallInfo}
class E_D_Bus extends Bundle{
  val D_stallInfo = Input(new StallInfo)
  val grfReadBus = Input(new GRFReadBus)
  val aluInBus = Input(new ALUInBus)
  val E_stallInfo = Output(new StallInfo)
}
class E_M_Bus extends Bundle{
  val E_stallInfo = Output(new StallInfo)
  val M_stallInfo = Input(new StallInfo)
}
class ExecuteStage extends Module{
  val io = IO(new Bundle{
    val D_Bus = new E_D_Bus
    val M_Bus = new E_M_Bus
  })
  val alu = new ALU
  val aluInBus = WireInit(io.D_Bus.aluInBus)//需要进行转发
  val aluOut = alu.io.out

  alu.io.in := aluInBus

  val rs = io.D_Bus.grfReadBus.rs
  val rt = io.D_Bus.grfReadBus.rt

  val E_stallInfo = RegInit(0.U.asTypeOf(new StallInfo))//reg
  val M_stallInfo = io.M_Bus.M_stallInfo

  val E_regWE = E_stallInfo.grfWriteBus.writeEnable
  val E_regID = E_stallInfo.grfWriteBus.writeID
  val E_regData = E_stallInfo.grfWriteBus.writeData
  val E_T = E_stallInfo.T

  val M_regWE = M_stallInfo.grfWriteBus.writeEnable
  val M_regID = M_stallInfo.grfWriteBus.writeID
  val M_regData = M_stallInfo.grfWriteBus.writeData
  val M_T = M_stallInfo.T

  aluInBus.rsData := MuxCase(io.D_Bus.aluInBus.rsData,Seq(
    (rs =/= 0.U && E_regWE && E_regID === rs && E_T === 0.U) -> E_regData,
    (rs =/= 0.U && M_regWE && M_regID === rs && M_T === 0.U) -> M_regData,
  ))
  aluInBus.rtData := MuxCase(io.D_Bus.aluInBus.rtData,Seq(
    (rt =/= 0.U && E_regWE && E_regID === rt && E_T === 0.U) -> E_regData,
    (rt =/= 0.U && M_regWE && M_regID === rt && M_T === 0.U) -> M_regData,
  ))


}
